Why Capacitors Moved Inside
AI chip power has climbed toward the kilowatt range, and when load spikes, current demand swings violently on a nanosecond scale. If delivery lags, you get voltage droop and noise — a throttle at best, a failure at worst. Capacitors cover that "too late" window, and the closer they sit to the die, the shorter the loop. So they migrated: from the PCB into the package substrate, the interposer, even directly beneath the die. The parameter that matters isn't capacitance — it's ESL, the wall that blocks current at high frequency.
Layered, Not Replaced
Let's break one myth first: silicon capacitors do not replace MLCCs — the division of labor between them is really a division by distance. MLCCs: ESL around 1nH, over 100μm thick, costing cents, handling broad board-level filtering and regulation, with tens of thousands to hundreds of thousands per AI rack. Silicon capacitors: built directly on silicon with semiconductor processes, ESL below 10pH (two orders of magnitude lower), thin enough (under 40μm) to be embedded in the package, handling the closest, highest-frequency decoupling beside the GPU, ASIC, and HBM. MLCCs are the reservoir outside the neighborhood; silicon capacitors are the fuel injector on the engine.
Routes: planar (MIM/MIS — most mature, limited density) → deep trench, DTC (2000–5000nm trenches, 800+ nF/mm², already 61.3% of global silicon capacitor shipments in 2025 and projected at 67.8% in 2026 — today's dominant route) → via-integrated, VIC (reusing TSV structures for roughly 10x the density, in accelerated adoption). Signals: Samsung Electro-Mechanics signed a long-term silicon capacitor contract worth about KRW 1.5 trillion (roughly RMB 6.8 billion) in May 2026 for 2027–2028 delivery — the largest single order ever; NVIDIA Rubin lists embedded silicon capacitors as standard, with TSMC integrating eDTC and IVRs into the CoWoS interposer; LG Innotek showcased an FC-BGA substrate-embedded solution; Morgan Stanley estimates a 57% global supply shortfall in 2026.
My Take
First, capacitors are moving from supporting cast to strategic component — once priced in cents and parked at the bottom of the BOM, now priced in dollars and written into the process definition of advanced packaging. Second, the moat is in process, not design — DTC comes down to high-aspect-ratio trench etching, ALD ultrathin dielectric deposition, and thin-film metallization: a pure micro-nano manufacturing problem. Whoever does it reliably gets to play. Third, do not mythologize — silicon capacitors will not replace MLCCs; calling them the "MLCC killer" is the biggest misreading.
